[Ti] New 15" 1.25 GHz PowerBook

[John Griffin]

OK, here is what someone said in the Apple Discussion area:

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There is no need for L3 cache anymore.  L3 cache was only there to help
compensate for the low bus bandwidth.  The L3 ran at 133Mhz.  Now the Bus
bottleneck is gone.  To Put 133Mhz L3 cache in there would BECOME the new
bottleneck in an outwise DDR speed memory pipeline.  This is why P4 etc has
no L3. 

The new system will rock, as having no more
133MHz-memory-bandwidth-bottleneck will mean the Altivec can finally flex
some serious muscle.  I just wish I could justify buying a new 15incher....

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There are some benchmarks posted already at:

http://www.barefeats.com/al15.html

jg