> While L3 cache is nice, L2 cache is what's important. When it comes to > L2 cache, while speed is nice, size is what is important. While Apple says > that 256kb of L2 cache at full processor speed performs as well as 1 MB cache > at 1/2 or 1/3 processor speed, for big number crunching this ends up not being > true; a larger cache. The old 500 MHz CPU most likely had 1 MB of L2 cache. > The new CPU upgrade probably only has 256kb of L2 cache. Sneaky, huh? But they *did* add a Level-3 cache on the PowerMac line -- does that make up for the smaller L2 cache? I don't know for sure (I'm no expert on processors), but I'd think it would help. > Cycle for cycle, the new generation of G4 processors are not as effcient > as the original G4 processors. Remember the Motorola G4 processor snafu? G4 > chips could not be clocked faster than 500 MHz. (Well they could, but Motorola > could not produce enough error-free chips.) In order to get around that issue, > Motorola redesigned the G4 architeture in order to increase the chip's clock > speed. (I think it went from a 4 stage pipeline to a 7 stage pipeline.) While > this enabled faster and faster G4 clock speeds, there was a trade-off in > processor efficency. Cycle for cycle, your old 500 MHz gets more work done > than your upgrade. Actually I think it went from 7 stages to 10. Anyone remember the big show in January 2001 when Apple showed the differences between the G4's pipeline and the P4's? They showed the G4's 7 stages finishing faster than the P4's 20 stages... Then they go and up the number of stages to 10? Actually, the current crop of high-speed G4s may have even more stages than that... To get the higher clock frequencies. Food for thought.