[Ti] New 15" 1.25 GHz PowerBook

[Tom R. no spam]

Cf KnowledgeBase 51910, the glossary Cache Memory entry,
says L2 used to be off CPU, now L2 is on CPU and L3 is
off CPU.  Somewhere recently I read an explanation, I
recall by Apple, why they were dropping L3 in--maybe?--
G5 units?  It had to do with cache access bus speeds, as
I recall.  I'm not sure if I saw this at an Apple web
site, or in IBM web site material re the chip Apple
calls the G5, or ...?.  I didn't see it in a quick search
just now on "L3 cache" at Apple's Support web page.

On Wed, 17 Sep 2003, Chris Rock wrote:

> it was 256k l2 and 1mb L3, now it is 512k L2
>
> L2 runs at core speed, L3 ran at a divider of core speed.
>
> Has nothing to do with the system bus, as they are both on die ( on the
> cpu ) all transactions were done inside the cpu, hence the reasoning for
> a  L2 or L3 in the first place, to reduce the cpu from having to hit
> main memory as much for reused information.
 . . .